Integrated circuit devices are an important part of many electronic devices, where the operation of an electronic device as a whole depends upon the operation of the integrated circuit devices. Data transmission is an important element of many integrated circuit devices. The speed and reliability of data transmission impacts the operation of an electronic device. Data can be transmitted as serial data or parallel data. Serializer-Deserializers (Serdes) transceivers, also known as Multi-Giga-bit Transceivers, are widely used to communicate digital data over backplanes at extremely high speeds. Receivers of Serdes transceivers have two key functional blocks, including an Equalization block which is responsible for opening up the eyes of a data signal, and a Clock and Data Recovery (CDR) block which is responsible for recovering the clock from the data so the eyes can be optimally strobed.
Equalization is necessary because backplane channels have frequency-dependent losses that give inter-symbol interference (ISI), causing the eyes to close down. CDR is necessary because, in a Serdes transceiver, the clock timing information is embedded in the data itself. This approach removes the delay-matching requirement (between data and clock) of a traditional parallel bus. However, conventional techniques of enabling a Serdes transceiver can be costly to implement and have a number of drawbacks.